相关阅读Design Compilerhttps://blog.csdn.net/weixin_45791458/category_12738116.html?spm1001.2014.3001.5482目录独热码编码的状态机设置了变量的独热码编码的状态机使用反向case语句的独热码编码的状态机使用反向case语句并设置了变量的独热码编码的状态机使用反向case语句并使用综合指令的独热码编码的状态机众所周知使用独热码编码状态机的好处是能够减少下一状态组合逻辑的复杂程度但笔者在使用Design Compiler进行测试时却发现结果似乎与预料的不一致本文将对此进行讨论。独热码编码的状态机例1展示的是一个简单的用独热码编码的状态机。// 例1 module onehot_fsm ( input wire clk, input wire reset, input wire start, output reg done ); parameter IDLE 4b0001; parameter LOAD 4b0010; parameter EXECUTE 4b0100; parameter DONE 4b1000; reg [3:0] state, next_state; always (posedge clk or posedge reset) begin if (reset) state IDLE; else state next_state; end always (*) begin case (state) IDLE: next_state (start) ? LOAD : IDLE; LOAD: next_state EXECUTE; EXECUTE: next_state DONE; DONE: next_state IDLE; default: next_state IDLE; endcase end always (*) begin done (state DONE); end endmodule如果直接进行综合则会发现下一状态组合逻辑依旧使用全译码实现如图1所示。图1 状态机的全译码实现图1所示电路的面积报告如下所示。**************************************** Report : area Design : onehot_fsm Version: W-2024.09-SP2 Date : Wed Aug 6 02:58:26 2025 **************************************** Information: Updating design information... (UID-85) Library(s) Used: fast (File: /home/zhangchen/Multiplier_Booth_STG_0/fast.db) Number of ports: 4 Number of nets: 18 Number of cells: 15 Number of combinational cells: 11 Number of sequential cells: 4 Number of macros/black boxes: 0 Number of buf/inv: 3 Number of references: 8 Combinational area: 36.691201 Buf/Inv area: 6.350400 Noncombinational area: 60.681601 Macro/Black Box area: 0.000000 Net Interconnect area: undefined (No wire load specified) Total cell area: 97.372802 Total area: undefined设置了变量的独热码编码的状态机在咨询了Synopsys的AE后他告诉我在读取RTL设计前将fsm_auto_inferring变量设置为true图2是这样做之后的综合结果可以看出下一状态组合逻辑使用独热译码实现。图2 状态机的独热译码实现图2所示电路的面积报告如下所示可以看出其中的组合逻辑的数量和面积都减少了。**************************************** Report : area Design : onehot_fsm Version: W-2024.09-SP2 Date : Wed Aug 6 03:07:29 2025 **************************************** Information: Updating design information... (UID-85) Library(s) Used: fast (File: /home/zhangchen/Multiplier_Booth_STG_0/fast.db) Number of ports: 4 Number of nets: 11 Number of cells: 8 Number of combinational cells: 4 Number of sequential cells: 4 Number of macros/black boxes: 0 Number of buf/inv: 2 Number of references: 5 Combinational area: 12.700800 Buf/Inv area: 4.233600 Noncombinational area: 60.681601 Macro/Black Box area: 0.000000 Net Interconnect area: undefined (No wire load specified) Total cell area: 73.382401 Total area: undefined使用反向case语句的独热码编码的状态机如果换一种RTL风格表示会发生什么例2展示的也是一个用独热码编码的状态机但与例1不同是这里使用了反向case语句即case expression为常量而case item为变量。// 例2 module onehot_fsm ( input wire clk, input wire reset, input wire start, output reg done ); parameter IDLE 4b0001; parameter LOAD 4b0010; parameter EXECUTE 4b0100; parameter DONE 4b1000; reg [3:0] state, next_state; always (posedge clk or posedge reset) begin if (reset) state IDLE; else state next_state; end always (*) begin case (1b1) state[0]: next_state (start) ? LOAD : IDLE; // IDLE state[1]: next_state EXECUTE; // LOAD state[2]: next_state DONE; // EXECUTE state[3]: next_state IDLE; // DONE default: next_state IDLE; endcase end always (*) begin done state[3]; end endmodule图3是fsm_auto_inferring变量设置为false时的综合结果可以看出下一状态组合逻辑使用全译码实现。图3 反向case语句的综合结果图3所示电路的面积报告如下所示。**************************************** Report : area Design : onehot_fsm Version: W-2024.09-SP2 Date : Wed Aug 6 03:25:34 2025 **************************************** Information: Updating design information... (UID-85) Library(s) Used: fast (File: /home/zhangchen/Multiplier_Booth_STG_0/fast.db) Number of ports: 4 Number of nets: 13 Number of cells: 10 Number of combinational cells: 6 Number of sequential cells: 4 Number of macros/black boxes: 0 Number of buf/inv: 2 Number of references: 6 Combinational area: 20.462400 Buf/Inv area: 4.233600 Noncombinational area: 60.681601 Macro/Black Box area: 0.000000 Net Interconnect area: undefined (No wire load specified) Total cell area: 81.144001 Total area: undefined使用反向case语句并设置了变量的独热码编码的状态机图4是将fsm_auto_inferring变量设置为true时的综合结果可以发现此时该变量的设置没有任何作用下一状态组合逻辑依旧使用全译码实现。图4 反向case语句的综合结果图4所示电路的面积报告如下所示。**************************************** Report : area Design : onehot_fsm Version: W-2024.09-SP2 Date : Wed Aug 6 03:33:01 2025 **************************************** Information: Updating design information... (UID-85) Library(s) Used: fast (File: /home/zhangchen/Multiplier_Booth_STG_0/fast.db) Number of ports: 4 Number of nets: 13 Number of cells: 10 Number of combinational cells: 6 Number of sequential cells: 4 Number of macros/black boxes: 0 Number of buf/inv: 2 Number of references: 6 Combinational area: 20.462400 Buf/Inv area: 4.233600 Noncombinational area: 60.681601 Macro/Black Box area: 0.000000 Net Interconnect area: undefined (No wire load specified) Total cell area: 81.144001 Total area: undefined这是因为反向case语句无法被Design Compiler识别为状态机即使将fsm_auto_inferring变量设置为true也无法被提取并进行优化可以在读取RTL设计后使用report_fsm命令查看状态机是否被识别。使用反向case语句并使用综合指令的独热码编码的状态机例2的一个问题在于Design Compiler并没有成功推导出状态机是独热编码的导致其认为state的各位存在优先级parallel_case综合指令用于表示多个case分支是平行的具体介绍可以参考下面的博客。HDL Compilerparallel_case综合指令的使用https://chenzhang.blog.csdn.net/article/details/148783195例3给出了修改后的代码。// 例3 module onehot_fsm ( input wire clk, input wire reset, input wire start, output reg done ); parameter IDLE 4b0001; parameter LOAD 4b0010; parameter EXECUTE 4b0100; parameter DONE 4b1000; reg [3:0] state, next_state; always (posedge clk or posedge reset) begin if (reset) state IDLE; else state next_state; end always (*) begin case (1b1) //synopsys parallel_case state[0]: next_state (start) ? LOAD : IDLE; // IDLE state[1]: next_state EXECUTE; // LOAD state[2]: next_state DONE; // EXECUTE state[3]: next_state IDLE; // DONE default: next_state IDLE; endcase end always (*) begin done state[3]; end endmodule图5是此时的综合结果可以看出下一状态组合逻辑使用全译码实现。图5 反向case语句的综合结果图5所示电路的面积报告如下所示可以看出其中的组合逻辑的数量和面积都减少了。**************************************** Report : area Design : onehot_fsm Version: W-2024.09-SP2 Date : Wed Aug 6 03:56:01 2025 **************************************** Information: Updating design information... (UID-85) Library(s) Used: fast (File: /home/zhangchen/Multiplier_Booth_STG_0/fast.db) Number of ports: 4 Number of nets: 11 Number of cells: 8 Number of combinational cells: 4 Number of sequential cells: 4 Number of macros/black boxes: 0 Number of buf/inv: 1 Number of references: 6 Combinational area: 14.817600 Buf/Inv area: 2.116800 Noncombinational area: 60.681601 Macro/Black Box area: 0.000000 Net Interconnect area: undefined (No wire load specified) Total cell area: 75.499201 Total area: undefined